This invention relates to the field of computer systems. More particularly, a method and apparatus are provided for transferring multiple packets from hardware to software.
Traditionally, packets are forwarded from the hardware that receives them, such as a network interface or channel adapter, to a host computing device with the assistance of descriptors. For each packet, one or more completion descriptors are configured to describe the packet (e.g., storage location, size, type) so that the host device could retrieve and process it. Thus, for each packet received at the hardware, the host device would receive an interrupt from the hardware, read the associated descriptor(s), then go and retrieve the packet for further processing before turning to the next one.
However, communication rates have increased exponentially in recent history, and have out-paced increases in processor speed. As a result, it is becoming more and more difficult, if not impossible, for a host device to keep up with incoming packets. Part of the problem is the amount of processor time that is needed to consume a completion descriptor for each packet.
Methods have been developed for interrupt blanking or coalescing, in which a single interrupt may be signaled for multiple packets being transferred from hardware to software. However, even with these methods, the host computing device still must process a separate completion descriptor for each packet.
Therefore, there is a need for a method and apparatus for describing or forwarding multiple packets to a host device using a single descriptor and/or for simplifying the form of such a descriptor so that they can be processed faster.